Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity and power dissipation without modifying logical operation of the circuit. Clock signals are often used within ASIC and programmable logic integrated circuits (IC) to control the timing of switching events. Each sub-circuit within an IC may be clocked by a single distributed clock signal, for example, to provide synchronized processing. In some cases, however, not all sub-circuits within a circuit are required to be active at all times. For example, certain logic may not be needed to produce output at times when the output is not used by subsequent logic. In these instances, the sub-circuits that implement the logic do not require a continuous clock signal. Continuously providing a clock signal to a sub-circuit that does not require the continuous clock signal adds unnecessarily to the power consumption of the IC. For example, in CMOS implemented logic, the switching activity of the circuit determines the average power dissipation of the circuit. Average power dissipation can be computed by estimating the average switching activity. As such, designers may gate clock signals to avoid unnecessary switching and thereby reduce power consumption.
Clock gating generally requires designers to manually add gating logic to their design code to disable unnecessarily active elements. However, several issues make the manual addition of clock gating logic a difficult process. In determining gating logic care must be taken to ensure that circuit elements continue to produce logically correct output. This often requires intimate knowledge of the design itself and typically requires numerous changes to the design. Because circuit designs implemented in ASICs and programmable ICs often incorporate legacy and third party IP design cores, developers generally do not have sufficient familiarity with the design cores to manually develop meaningful clock-gating logic in a time-efficient manner. Unless the gains in power efficiency are sufficient and essential to the success of the design, the additional complexity and time can be prohibitive and may introduce unintended errors into the design.
The embodiments of the present invention may address one or more of the above issues.